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HI3300
TM
Data Sheet
March 2000
File Number
4822.1
3V 10-Bit, 20MSPS A/D Converter with Internal Voltage Reference
The HI3300 is a monolithic, 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The HI3300 features a 2-step parallel architecture to allow the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI3300 has excellent dynamic performance while consuming less than 40mW power at 20MSPS. The A/D only requires a single +3.0V power supply.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .20MSPS * Low Power at 20MSPS. . . . . . . . . . . . . . . . . . . . . . .40mW * Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3mW * Wide Full Power Input Bandwidth. . . . . . . . . . . . . 100MHz * On-Chip Sample and Hold Amplifiers * Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.3V
Applications
* Wireless Local Loop * PSK and QAM I&Q Demodulators
Ordering Information
PART NUMBER HI3300IN TEMP. RANGE (oC) PACKAGE SAMPLING RATE PKG. NO. (MSPS) Q48.7x7-S 20
* Medical Imaging * Wireless Communications Systems * Battery Powered Instruments
-40 to 85 48 Ld LQFP
Pinout
HI3300 48 LEAD LQFP TOP VIEW
DVDD AVDD AVDD AT TSTR DVSS AvDD AVSS CAL AVSS TS VIN
DO D1 D2 D3 D4 DVSS
DVDD
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
BE
AVDD AVSS
VRBS VRB VRBC VRMC VRTC VRT VRTS
AVDD AVSS
D5 D6 D7 D8 D9
RESET AVSS
TEST
LINV MINV
AvDD
AvDD CLK
TO
TIN
OE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
CE
HI3300 Block Diagram
VIN 38 S/H AMP + COARSE CORRECTION AND LATCH x8 12 D9 11 D8 10 D7 9 8 DAC COARSE COMPARATE AND ENCODE FINE FIN3 COMPARATE AND ENCODE FIND LATCH CALIBRATION UNIT D6 D5
VRT 28 VRTC 29
+ -
VRTS 27
VRMC 30 BE 36 VRBS 33
5 4 3 2 1
D4 D3 D2 D1 D0 (LSB)
VRB 32 VRBC 31
+ -
20 MINV 19 LINV 18 TEST MODE
CLK 22 OE 23 CE 24
TIMING GEN
AUTO CALIBRATION PULSE GENERATOR
42 CAL
15 RESET
2
HI3300
Absolute Maximum Ratings
Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . . . AVSS -0.5V to 4.5V (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVSS -0.5V to 4.5V Reference Voltage (VRT, VRB) . . . . . . . . AVDD +0.5V to AVSS -0.5V Input Voltage (Analog) (VIN) . . . . . . . . . . . . . . AVDD +0.5V to -0.5V Input Voltage (Digital) (VIH, VIL) . . . . . . AVDD +0.5V to AVSS -0.5V Output Voltage (Digital) (VOH, VOL). . . . DVDD +0.5V to DVSS -0.5V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 48 Ld LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage Range (AVDD, AVSS) . . . . . . . . . . . . 3.0V to 0.3V (DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 0.3V DVSS - AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage (VRB). . . . . . . . . 0.3 AVDD to 0.5 AVDDV (VRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 AVDD to 0.8 AVDDV Analog Input (VIN) . . . . . . . . . . . . . . . . . . . . . . . 0.9 Vp-p or More Clock Pulse Width (tPW1), (tPW0) . . . . . . . . . . . . . . . . 25ns (Min) Operating Ambient Temperature (TOPR) . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Maximum Conversion Rate Minimum Conversion Rate Supply Voltage Analog Digital Standby Current Analog Digital Reference Pin Current 1
fC = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, TA = 25oC SYMBOL fC max fC min IADD IDDD IAST IDST IRT1 IRB1 VRTS, VRBS: Open Between VRT and VRB CONDITIONS MIN. 20 TYP. 12 1.0 1.0 1.0 100 -100 2 -2 TBD 10 10k 500 TBD TBD 20 -20 MAX. 0.5 0.2 5 5 A A V MHz pF mV mA mA A A mA UNIT MSPS
fIN = 1.0kHz Triangular Wave Input fIN = 1.0kHz Triangular Wave Input
BE = High CE = AVDD
-
Reference Pin Current 2
IRT2 IRB2
BE = AVDD Between VRTC and VRBC
-
Analog Input Band Analog Input Capacitance Reference Resistance Value 1 Reference Resistance Value 2 Offset Voltage
BW CIN RREF1 RREF2 EOT EOB
-1dB
-
Between VRTS and VRT, VRT and VRB, VRB and VRBS Between VRTC and VRBC EOT = Theoretical Value - Measured Value EOB = Measured Value - Theoretical Value AVDD = 2.7 to 3.3V
0.7 -
Digital Input Voltage
VIH VIL
Analog Input Current
AIH AIL
VIN = 2V VIN = 1V AVDD = 3.3V VIH - AVDD VIL = AVSS
-
Digital Input Current
IIH IIL
3
HI3300
Electrical Specifications
PARAMETER Digital Output Current fC = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, TA = 25oC (Continued) SYMBOL IOH IOL Digital Output Current IOZH IOZL Three-State Output Disable time Three-State Output Enable Time Integral Nonlinearity Error Differential Nonlinearity Error Differential Gain Error Differential Phase Error Output Data Delay Sampling Delay SNR tPEZ tPEZ EL ED DG DP tDL tSD SNR fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 7MHz fIN = 10MHz SFDR SFDR fIN = 100kHz fIN = 500kHz fIN = 1MHz fIN = 3MHz fIN = 7MHz fIN = 10MHz CL = 20pF NTSC 40 IRE Mod Ramp, fC = 14.3MSPS OE = AVSS DVDD = 2.7V OE = AVDD DVDD = 3.3V CONDITIONS VOH = DVDD -0.4V VOL = 0.4V VOH = DVDD VOL = 0V MIN. 1.0 1.0 TYP. 2 2 1.0 0.5 TBD TBD 3 2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD MAX. 1.0 1.0 ns ns LSB LSB % Deg ns ns dB dB dB dB dB dB dB dB dB dB dB dB A UNIT mA
Clock not Synchronized for Active High Impedance Clock not Synchronized For High Impedance Active
4
HI3300 Timing Diagrams
tPW1 tPW0
CLOCK
1.5V
tSD N +1 ANALOG INPUT N N +2 tDL N +3 N +4
DATA OUTPUT
N -3
N -2
N -1
N
1.5V
NOTE:
: Indicates point at which analog data is sampled. FIGURE 1. TIMING CHART 1
tPEZ 1.5V OUTPUT ENABLE (OE) 1.5V
tPZE 1.5V
DATA OUTPUT
ACTIVE
HIGH IMPEDANCE
ACTIVE
FIGURE 2. TIMING CHART 2
5
HI3300
S
Pin Description
PIN NO. 1 to 5 8 to 12 SYMBOL D0 to D9
DVDD
EQUIVALENT CIRCUIT
DESCRIPTION D0 (LSB) to D9 (MSB) output.
DVSS
6, 48 7, 47 13 14 15
DVSS DVDD TO TIN RESET
AVDD
Digital Ground. Digital Power. Test signal output. High impedance when TS = high. Test signal input. Normally fixed to AVDD or AVSS . Calibration circuit reset and startup calibration restart.
15
AVSS
16, 25, 34, 4, 46 17, 21, 26, 35, 40, 43, 45 18
AVSS AVDD TEST MODE
Analog Ground. Analog Power. N/C Do not use.
AVDD
18
AVSS
19
LINV
AVDD
Output Inversion. High: D0 to D8 are inverted and output. Low: D0 to D8 are normal output.
19
AVSS
6
HI3300 Pin Description
PIN NO. 20 MINV
AVDD
(Continued) EQUIVALENT CIRCUIT DESCRIPTION Output Inversion. High: D9 is inverted and output. Low: D9 is Normal output.
SYMBOL
20
AVSS
22
CLK
AVDD
Clock Input.
22
AVSS
23
OE
AVDD
D0 to D9 Output Enable. Low: Output Active. High: High Impedance state.
23
AVSS
24
CE
AVDD
Chip Enable. Low: Active state. High: Standby state.
24
AVSS
7
HI3300 Pin Description
PIN NO. 27 28 29 30 31 32 33 36 VRTS VRT VRTC VRMC VRBC VRB VRBS BE
28 + AVSS AVDD 27 AVDD
(Continued) EQUIVALENT CIRCUIT DESCRIPTION Self bias (Reference top). Reference top. Reference top output. Reference middle output. Reference bottom output. Reference bottom. Self bias (reference bottom). Bias enable.
SYMBOL
AVSS AVDD
29
AVSS AVDD
30
AVSS AVDD
31
AVSS AVDD
32
+ -
AVSS AVDD
33
AVDD
AVSS
36
AVSS
37
TSTR
Test signal input. Tie to AVDD or AVSS .
8
HI3300 Pin Description
PIN NO. 44 38 AT VIN
AVDD
(Continued) EQUIVALENT CIRCUIT No Connect Analog input. DESCRIPTION
SYMBOL
38
AVSS
42
CAL
AVDD
Calibration pulse input.
42
AVSS
39
TS
Test signal input. Normally fixed to AVDD.
9
HI3300 Digital Output
The following table shows the correlation between the analog input voltage and the digital output code (TESTMODE = 1, LINV, MINV = 0).
TABLE 1. INPUT SIGNAL VOLTAGE VRT DIGITAL OUTPUT CODE STEP 1023 * * * * 512 511 MSB 1111111111 LSB
* * * * * * * * * * * *
VRB
* * * *
1000000000 0 1 1 1 1 1 1 11 1
* * * *
0
* * * *
0000000000
The following table shows the output state for the combination of TESTMODE, LINV, and MlNV states.
TABLE 2. TEST MODE 1 1 1 1 0 0 0 0 LlNV 0 1 0 1 0 1 0 1 MlNV 0 0 1 1 0 0 1 1 D0 P N P N 1 0 1 0 D1 P N P N 0 1 0 1 D2 P N P N 1 0 1 0 D3 P N P N 0 1 0 1 D4 P N P N 1 0 1 0 D5 P N P N 0 1 0 1 D6 P N P N 1 0 1 0 D7 P N P N 0 1 0 1 D8 P N P N 1 0 1 0 D9 P P N N 0 0 1 1
NOTE: P: Forward-phase output; N: Inverted output.
10
HI3300 Application Circuit 1
When not using self-bias and the internal bias circuits and supplying the reference voltage from an external source.
1V AVDD 2V AVDD
AVSS 36 35 34 33 32 31 30 29 28 27 26 25 VRBS VRTS AVSS VRBC VRMC VRTC AVDD AVDD AVSS BE VRB VRT AVDD 2.0V 1.0V SIGNAL INPUT
37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL CALIBRATION PULSE 43 AVDD 44 AT 45 AVDD AVSS DVDD DVSS 46 AVSS 47 DVDD
CE 24 OE 23 CLK 22 CLOCK PULSE
AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 DVDD DVSS TO 13 D5 D6 D7 D8 D9 AVSS RESET PULSE AVDD
48 DVSS D0 D1 D2 D3 4 D4 5
1
2
3
6
7
8
9
10 11 12 : 0.1F POWER SUPPLY DECOUPLERS
DVSS DVDD
DIGITAL OUTPUT
NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
11
HI3300 Application Circuit 2
When not using self-bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source.
AVDD
1V
2V
AVDD
AVSS 36 35 34 33 32 31 30 29 28 27 26 25 VRBS VRTS AVSS VRBC VRMC VRTC AVDD AVDD AVSS BE VRB VRT AVDD 2.0V 1.0V SIGNAL INPUT
37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL CALIBRATION PULSE 43 AVDD 44 AT 45 AVDD AVSS DVDD DVSS 46 AVSS 47 DVDD
CE 24 OE 23 CLK 22 CLOCK PULSE
AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 DVDD DVSS TO 13 D5 D6 D7 D8 D9 AVSS RESET PULSE AVDD
48 DVSS D0 D1 D2 D3 4 D4 5
1
2
3
6
7
8
9
10 11 12 : 0.1F
DVSS DVDD
DIGITAL OUTPUT
NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
12
HI3300 Application Circuit 3
When not using self bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source.
AVDD
AVDD
AVSS 36 35 34 33 32 31 30 29 28 27 26 25 VRBS VRTS AVSS VRBC VRMC VRTC AVDD AVDD AVSS BE VRB VRT AVDD 2.0V 1.0V SIGNAL INPUT
37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL CALIBRATION PULSE 43 AVDD 44 AT 45 AVDD AVSS DVDD DVSS 46 AVSS 47 DVDD
CE 24 OE 23 CLK 22 CLOCK PULSE
AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 DVDD DVSS TO 13 D5 D6 D7 D8 D9 AVSS RESET PULSE AVDD
48 DVSS D0 D1 D2 D3 4 D4 5
1
2
3
6
7
8
9
10 11 12 : 0.1F
DVSS DVDD
DIGITAL OUTPUT
NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of these use of the circuits or for any infringement of third party patent and other right due to same.
13
HI3300 Calibration Function
Activating Startup Calibration
To achieve superior linearity, the HI3300 has a built-in calibration circuit. Startup calibration must be activated when the power supply and reference voltage have risen and stabilized. Care should be taken as only the upper five bits may be output in the worst case if startup calibration is not activated. Startup calibration can be activated either at the rise of the RESET pin (Pin 15) or at the fall of the CE pin (Pin 24). The startup calibration activation method for each case is shown in Figure 3. As shown in the Figure 3, startup calibration must be activated after the supply voltage has risen and stabilized (full scale of 90% or more). After activation, startup calibration is performed for an interval of about 33,000 clocks. Therefore, care should be taken as the output data during this interval (about 2.3ms at 14.3MHz) cannot be used.
Calibration Pulse Supply
The IC's operating status with changes due to fluctuations in the supply voltage and ambient temperature during use can be constantly monitored and then compensated appropriately by inputting a pulse at regular intervals to the CAL pin (Pin 41). Figure 4 shows the timing chart.
B. WHEN USING CE [V] 3 AVDD
A. WHEN USING RESET [V] AVDD 3 VRT
VRT
VRB
VRB
0
[t]
0
[t]
H RESET L H L
RESET
H L H
CE STARTUP CALIBRATION
CE STARTUP CALIBRATION
L
33,000 CLK
33,000 CLK
FIGURE 3. STARTUP CALIBRATION ACTIVATION METHODS
10ns OR MORE 7CLOCK CLK
CAL
1CLOCK OR MORE
D0 TO D9
N-3
N-2
N-1
N
N +5
FIGURE 4. CALIBRATION TIMING CHART
14
HI3300
Calibration starts when the fall of the pulse input to the CAL pin (Pin 41) is detected at the clock rise. At this time, the comparator is used in an exclusive manner for a four clock interval. So, the output data holds the immediately previous data for a four clock interval after seven clocks from the rise of the clock where the fall of the calibration pulse was detected, and then the data during this interval is missing. Therefore, the effects of this function can be avoided by inputting a sync or other signal as the calibration pulse so that calibration is performed outside of the interval of the actually used video signal. An input example is shown below.
Input ever H Sync
INPUT CLK CAL
Input ever V Sync
INPUT
CLK RESET CAL
Latch-up
Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power-ON time lag.
Board
To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately.
15
HI3300 Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D D1
Q48.7x7-S
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B D MIN 0.056 0.000 0.006 0.347 0.272 0.347 0.272 0.012 48 0.020 BSC MAX 0.066 0.007 0.010 0.362 0.279 0.362 0.279 0.027 MILLIMETERS MIN 1.40 0.00 0.15 8.80 6.90 8.80 6.90 0.30 48 0.500 BSC MAX 1.70 0.20 0.26 9.20 7.10 9.20 7.10 0.70 NOTES 5 2 3, 4 2 3, 4 6 Rev. 1 4/95 NOTES:
A SEATING PLANE
E
E1
D1 E E1 L e
PIN 1
N e
-H-
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. "N" is the number of terminal positions.
0.10 0.004 0.24 M B 0o-10o A1 -C-
L 0.107/0.177 0.004/0.007
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
16

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